Cache coherence & ownership
Keep cached copies of a memory location consistent across processors.
A write can require ownership of an entire cache line.
Tracks permission and modification.
Make a cache miss
A cache fetches a whole line. Locality reuses it; conflicting mappings can evict useful data even before total capacity is exhausted.
What this model includes
One read-only cache, 64-byte lines, LRU replacement, eight total lines, eight-byte elements, 32 accesses. No prefetching or multilevel effects.
What happens inside
Track shared copies
A coherent system tracks where a line is cached and whether a copy is modified. MESI-like protocols use states such as modified, exclusive, shared, and invalid; real protocols add details. A writer obtains permission and may invalidate other copies. A modified owner may supply data without DRAM.
Distinguish ordering from agreement
Coherence governs copies of a location; consistency defines allowed ordering across operations and locations. Store buffers and relaxed ordering can make writes become visible later than source order suggests. Correct synchronization requires the language and hardware memory models together.
What this means for your code
Low-level engineer
Use atomic and barrier primitives with the intended scope. Cache coherence alone does not provide a happens-before relation in a language.
Software developer
Reduce cross-thread writable sharing. Even correct atomic operations can generate expensive coherence traffic under contention.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.