silicon atlasTHE HARDWARE REFERENCE
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CHOOSE A QUESTION TO WORK TOWARD

Connect what you know.

Four suggested reading paths. Nothing is locked. Skip what you know, and revisit anything you need.

0/9 read

Software developer

Understand where time goes before changing the code.

  1. 1Anatomy of a CPU core
  2. 2Registers, caches & the memory hierarchy
  3. 3Latency, bandwidth & memory channels
  4. 4Virtual memory, page tables & TLBs
  5. 5Cores, threads & SMT
  6. 6False sharing & cache-line contention
  7. 7Amdahl’s law & parallel scaling
  8. 8IPC, latency & real performance
  9. 9The roofline model
TRY TO EXPLAIN

Explain a cache miss, choose a data layout, size a worker pool, and design a trustworthy performance comparison.

0/13 read

Low-level & systems engineer

Learn the contracts between instructions, the OS, and devices.

  1. 1Bits, integers & floating point
  2. 2ISA, microarchitecture & ABI
  3. 3Registers, flags & the stack
  4. 4Pipelines & instruction hazards
  5. 5Out-of-order execution & renaming
  6. 6Cache coherence & ownership
  7. 7Atomics, barriers & memory ordering
  8. 8Virtual memory, page tables & TLBs
  9. 9PCIe, lanes & device links
  10. 10DMA, MMIO & IOMMUs
  11. 11Interrupts, timers & polling
  12. 12Firmware, boot & the operating system
  13. 13Privilege, isolation & side channels
TRY TO EXPLAIN

Trace an instruction, reason about publication, map a DMA buffer, and describe boot and interrupt ownership.

0/10 read

GPU & compute engineer

Follow thread groups, transactions, and the actual bottleneck.

  1. 1SIMD & vector instructions
  2. 2Anatomy of a GPU
  3. 3SIMT, warps & wavefronts
  4. 4GPU memory & coalescing
  5. 5Occupancy & latency hiding
  6. 6Commands, queues & GPU synchronization
  7. 7The graphics pipeline
  8. 8Ray tracing & RT hardware
  9. 9Unified memory & shared addressing
  10. 10The roofline model
TRY TO EXPLAIN

Explain divergence, arrange coalesced loads, assess occupancy, and synchronize an asynchronous command stream.

0/14 read

Hardware & accelerator engineer

Connect logic, physical timing, data flow, and energy.

  1. 1Transistors & CMOS
  2. 2Logic gates & Boolean algebra
  3. 3Clocks, flip-flops & state
  4. 4ALUs, FPUs & execution ports
  5. 5Inside DRAM
  6. 6ECC, parity & memory reliability
  7. 7SoCs, chiplets & packages
  8. 8Tensor cores, MAC arrays & systolic data flow
  9. 9Quantization, precision & TOPS
  10. 10NPUs & neural engines
  11. 11DSPs, media engines & fixed-function blocks
  12. 12FPGAs, ASICs & programmable logic
  13. 13Clocks, voltage, boost & cooling
  14. 14Process nodes, yield & packaging
TRY TO EXPLAIN

Build a truth table, explain clock crossings, describe a matrix data flow, and compare precision and power under explicit assumptions.

CONCEPTS

Transistors & CMOSA tiny voltage-controlled switch. Billions of them become a computer.
Anatomy of a CPU coreA core is a complete instruction engine, not just an arithmetic unit.
Anatomy of a GPUMany execution lanes share control machinery to process parallel work.
Inside DRAMA capacitor holds a bit. A controller keeps billions of them readable.
NPUs & neural enginesDedicated data paths turn repeated tensor operations into efficient hardware work.
SoCs, chiplets & packagesA system is more than a CPU. Integration changes how its parts communicate.
Logic gates & Boolean algebraSimple truth tables become selectors, adders, and control circuits.
Bits, integers & floating pointThe same bits can represent a number, an instruction, or a color.
Clocks, flip-flops & stateA clock separates what a circuit remembers from what it computes next.
ISA, microarchitecture & ABIThe instruction contract, its implementation, and the rules for calling code.
From source to machine codeYour code becomes data flow, instructions, and a contract with the runtime.
Pipelines & instruction hazardsOverlap stages of different instructions instead of finishing one at a time.
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