Clocks, voltage, boost & cooling
Performance operates inside electrical, thermal, and shared power limits.
A short burst and an hour of heavy work can run at very different clocks.
A timed execution region.
Turn up the clock
Dynamic switching power scales roughly with voltage squared and frequency. Leakage, temperature, and idle behavior also matter in real chips.
What this model includes
Normalized dynamic switching power with constant activity and capacitance. Voltage and frequency are independent controls here, unlike a real DVFS operating table.
What happens inside
Pay for switching
Dynamic switching power scales approximately with activity, capacitance, voltage squared, and frequency. Leakage adds static consumption and varies with process and temperature. Raising frequency often requires voltage changes to meet timing. Clock gating suppresses switching; power gating cuts power to idle domains with wake-up costs.
Maintain a safe operating point
DVFS changes operating voltage and frequency under platform policy. Boost uses available power, current, and thermal headroom. The cooling path carries heat from die through package and heatsink to the environment. Sustained clocks depend on workload, ambient conditions, and other active blocks. TDP is not a universal maximum-power definition.
P_dynamic ≈ α · C · V² · fWhat this means for your code
Low-level engineer
Consider idle states, wake latency, power domains, and sustained operating tables. Frequency controls do not override safe physical limits.
Software developer
Benchmark long enough to see sustained behavior. Batching may save energy by finishing sooner, but latency constraints can favor smaller work units.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.