What is behind the name?

CPU core

An instruction engine with its own execution context and substantial control hardware.

Physical cores, SMT contexts, cache topology, and sustained performance.

P-core / E-core

Core designs with different performance, area, and energy tradeoffs.

Exact microarchitecture, ISA features, scheduler behavior, and power limits.

Prime / Super / Ultra core

A vendor’s description of a high-performance core or configuration. It is not a standard ISA category.

Distinct design or frequency bin? Which cache and sustained clocks?

Intel Core / Core Ultra

Product-family branding. It does not uniquely specify a core design or NPU capability.

Generation, SKU, core mixture, supported instructions, and integrated blocks.

Ryzen / Zen

Ryzen is a processor brand; Zen names CPU microarchitecture generations. A model number needs decoding.

Actual Zen generation, core topology, cache, and power configuration.

Apple M / Neural Engine

M names a system-on-chip family; Neural Engine names its neural acceleration block.

Exact chip and model support, memory configuration, and measured inference.

Oryon / Adreno / Hexagon

Qualcomm names for CPU, GPU, and DSP/NPU-related implementations, respectively.

Chip generation and actual block capabilities, not just the family names.

CUDA core / Stream processor

Vendor resource counts associated with GPU arithmetic lanes, not complete CPU cores.

Architecture, operation format, issue rate, memory traffic, and achieved throughput.

SM / CU / WGP

Execution-group structures: streaming multiprocessor, compute unit, or workgroup processor. They differ by design.

Lane organization, scheduling, local storage, occupancy, and generation.

Tensor Core

A specialized matrix operation engine within a GPU implementation.

Supported formats and tile shapes, accumulator precision, dense/sparse rate.

RT Core / Ray Accelerator

Dedicated resources for selected ray traversal and intersection work.

Scene, ray count, BVH cost, shading, resolution, and reconstruction settings.

TOPS / TFLOPS

Peak operation rates. Meaning depends on precision, operation counting, and sparsity assumptions.

Same precision, dense/sparse conditions, accuracy, and complete workload.

GHz / Boost / Turbo

Clock rate and a policy for temporarily using available operating headroom.

Sustained clocks, cooling, active cores, workload, and power policy.

TDP / TBP

Vendor-defined thermal or power design figures. Definitions vary by product and company.

Measurement boundary, sustained limits, transient behavior, and actual wall power.

3 nm / 2 nm / Process node

A process-generation label, not a standardized literal transistor dimension.

Actual chip performance, density, leakage, SRAM scaling, and operating power.

Unified memory / Zero-copy

Shared memory or address abstractions, and avoiding a particular explicit copy. Mechanisms vary.

Physical residency, coherence, migration, access path, and synchronization.

DDR5 / LPDDR / GDDR / HBM

Memory families designed for different platform, energy, packaging, and bandwidth needs.

Bus width, channels, transfer rate, latency, capacity, and integration.

ECC / On-die ECC

Error protection with a specified code and boundary. Internal DRAM ECC covers a different path from system ECC.

Controller, DIMM, board, firmware support, and reported error coverage.

M.2 / NVMe / PCIe

Form factor, storage protocol, and interconnect, respectively. One name cannot substitute for the other two.

Device protocol, negotiated link, endurance, latency, and sustained speed.