Clocks, flip-flops & state
A clock separates what a circuit remembers from what it computes next.
Without state, a circuit can answer a question but cannot remember the answer.
Edge-sampled state.
Follow an instruction
Overlap improves throughput. Dependencies introduce bubbles unless the implementation can forward or do independent work.
What this model includes
Five-stage, single-issue teaching model. Dependent mode inserts two idle issue cycles per instruction; real forwarding and hazards vary.
What happens inside
Hold a value
Combinational logic derives an output from current inputs. Sequential logic also depends on stored state. A latch is level-sensitive; a flip-flop samples around a clock edge. Registers group storage bits. SRAM cells hold state through feedback while power remains, unlike DRAM’s periodically refreshed charge.
Meet a timing contract
Input data must be stable for a setup interval before sampling and a hold interval after it. The slowest register-to-register path constrains the clock period. Crossing unrelated clock domains can cause metastability; synchronizers reduce failure probability, while multi-bit data needs a suitable handshake or asynchronous FIFO.
What this means for your code
Low-level engineer
Check setup, hold, clock skew, and reset release. A two-flop synchronizer is for suitable single-bit signals, not arbitrary buses.
Software developer
State machines underpin protocols and device controllers. Ordering in your program is not proof that asynchronous hardware has completed an operation.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.