SoCs, chiplets & packages
A system is more than a CPU. Integration changes how its parts communicate.
Two components can share a package without sharing a coherent address space.
A single manufactured silicon piece.
Find the bottleneck
Low arithmetic intensity hits the memory ceiling. More data reuse can move the workload toward the compute ceiling.
What this model includes
An ideal upper bound with fixed peak compute and bandwidth. Ignores latency, overhead, cache-level traffic, and instruction mix.
What happens inside
Separate die, package, and board
A die is a piece of processed silicon. A package protects dies and connects them to the board through substrates, bumps, and pins. A chiplet is a die designed to participate in a multi-die system. Package-level interconnect still has latency, bandwidth, and power costs.
Integrate the system
An SoC can combine CPU clusters, GPU, accelerators, memory controllers, display engines, security blocks, and I/O. These share a fabric and power budget. RAM may sit on the board or in the same package; “SoC” does not imply that DRAM lives on the logic die.
Follow an access across the fabric
A fabric routes requests, arbitrates contention, and may maintain cache coherence. Integrated devices can share physical memory yet still require explicit fences and ownership transfer. Software must know the memory model, not just whether the chips are close together.
What this means for your code
Low-level engineer
Map topology, coherence domains, device apertures, interrupts, and clock/power domains. A physical block diagram is not a complete programming contract.
Software developer
Shared memory can reduce copies, but CPU, GPU, and NPU may compete for the same bandwidth. Profile concurrent work on the complete device.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.