Inside DRAM
A capacitor holds a bit. A controller keeps billions of them readable.
Reading a DRAM row disturbs it, so the chip restores what it just read.
One small charge represents a bit.
Open a memory row
The active row stays in sense amplifiers. Another access to it can skip activation; changing rows adds precharge and activation.
What this model includes
One bank, no refresh or overlap, fixed 14 ns command delays. Values illustrate order, not specifications for a DIMM.
What happens inside
Store charge in cells
A typical DRAM cell uses one access transistor and one capacitor. Charge leaks, requiring periodic refresh. Cells share wordlines and bitlines. A bank contains many rows, but usually only one row in that bank is active at a time.
Open a row, select columns
ACTIVATE connects a row to sense amplifiers, which detect and restore the small charge difference. Reads and writes select columns in the row buffer. A row hit skips reopening; a conflicting row needs precharge and another activation.
Coordinate channels and timings
The memory controller schedules commands across banks and channels while obeying timing and refresh constraints. DDR transfers data on both clock edges. MT/s is the transfer rate; capacity, sustained bandwidth, and first-access latency are separate properties.
What this means for your code
Low-level engineer
Distinguish tCL, tRCD, tRP, and tRAS. Address-to-bank mapping and controller scheduling make real latency more complex than one timing number.
Software developer
More RAM avoids paging when your working set is large. Extra capacity does not automatically speed up data that already fits. Access pattern and channel population matter.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.