silicon atlasTHE HARDWARE REFERENCE
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THE EXPERIMENT BENCHCHANGE. OBSERVE. UNDERSTAND.

Change something. See what happens.

Nine experiments. Real calculations. Start by changing a single thing.

LIVE EXPERIMENT

Make a cache miss

Runs on your device
BYTE ADDRESS0Block 0 → Set 0MISS
SET 0tag 0
SET 1·
SET 2·
SET 3·
SET 4·
SET 5·
SET 6·
SET 7·
Accesses1
Hit rate0%
Bytes fetched64
Select any access above, or step through the trace.

A cache fetches a whole line. Locality reuses it; conflicting mappings can evict useful data even before total capacity is exhausted.

What this model includes

One read-only cache, 64-byte lines, LRU replacement, eight total lines, eight-byte elements, 32 accesses. No prefetching or multilevel effects.

Go deeper into the mechanism

Change locality, capacity, and associativity.

CONCEPTS

Transistors & CMOSA tiny voltage-controlled switch. Billions of them become a computer.
Anatomy of a CPU coreA core is a complete instruction engine, not just an arithmetic unit.
Anatomy of a GPUMany execution lanes share control machinery to process parallel work.
Inside DRAMA capacitor holds a bit. A controller keeps billions of them readable.
NPUs & neural enginesDedicated data paths turn repeated tensor operations into efficient hardware work.
SoCs, chiplets & packagesA system is more than a CPU. Integration changes how its parts communicate.
Logic gates & Boolean algebraSimple truth tables become selectors, adders, and control circuits.
Bits, integers & floating pointThe same bits can represent a number, an instruction, or a color.
Clocks, flip-flops & stateA clock separates what a circuit remembers from what it computes next.
ISA, microarchitecture & ABIThe instruction contract, its implementation, and the rules for calling code.
From source to machine codeYour code becomes data flow, instructions, and a contract with the runtime.
Pipelines & instruction hazardsOverlap stages of different instructions instead of finishing one at a time.
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