Cache lines, sets & replacement
An address chooses a set, and a tag identifies the line inside it.
Two tiny data sets can fight for the same cache slots.
Position within a line.
Make a cache miss
A cache fetches a whole line. Locality reuses it; conflicting mappings can evict useful data even before total capacity is exhausted.
What this model includes
One read-only cache, 64-byte lines, LRU replacement, eight total lines, eight-byte elements, 32 accesses. No prefetching or multilevel effects.
What happens inside
Decode an address
A simple cache divides an address into line offset, set index, and tag. A direct-mapped cache has one slot per set; an N-way cache has N candidate slots. More associativity reduces some conflicts but costs comparison logic and energy. Real caches may hash addresses or use more complex indexing.
Handle misses and writes
Cold misses fetch unseen lines. Capacity misses exceed useful storage; conflict misses compete within sets. Replacement chooses a victim, often approximating recency. A write-back cache marks a line dirty and writes it later; a write-through policy propagates writes. Allocation and coherence rules add further behavior.
block = floor(address / line_bytes); set = block mod setsWhat this means for your code
Low-level engineer
Map strides against sets and page boundaries. Padding can remove a conflict but enlarge the working set; measure both effects.
Software developer
Blocking and data layout can reuse fetched lines. A large stride can waste most of every line even when the total array fits.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.