Know what the words mean.

Rules for calling functions, preserving registers, and connecting compiled code.

An execution unit for integer arithmetic and bit operations.

Useful operations per byte moved at a chosen memory boundary.

An access with defined indivisibility and concurrency semantics.

The amount of data transferred per unit time.

A PCI device configuration resource describing a memory or I/O window.

Grouping manufactured parts by tested operating characteristics.

Hardware that guesses future control flow before it is resolved.

Nested bounds that narrow a ray’s search for intersections.

A block transferred and tracked as a unit by a cache.

A die designed to participate in a multi-die system.

Logic built from complementary n-channel and p-channel devices.

Combining nearby GPU lane accesses into fewer memory transactions.

Rules that coordinate cached copies of a memory location.

Average cycles per instruction and instructions per cycle for a defined measurement.

One manufactured piece of processed silicon.

A device transfers data through a mapped memory path without CPU byte-by-byte copying.

Charge-based memory that needs refresh to retain data.

Changing operating voltage and frequency under platform policy.

Redundant information that detects or corrects specified error patterns.

Different writable data shares a coherence line and causes ownership contention.

Floating-point operations per second, for a specified format and counting convention.

Programmable logic and routing configured to implement a circuit.

An SSD mapping from logical storage addresses to physical flash pages.

Translates and constrains device-visible memory addresses.

The software-visible instruction and architectural state contract.

Generating machine code while a program is running.

Delay between a request and its usable result.

A configurable truth-table resource in programmable logic.

Multiply operands and add the product into an accumulator.

Device registers exposed through mapped CPU address ranges.

Transfer rate, which is distinct from the memory clock frequency.

Memory cost varies with processor and physical placement.

A queue-based command interface for nonvolatile storage.

Resident GPU work relative to a supported residency limit.

An address translation or access condition that requires OS handling.

A packet-based serial interconnect with negotiated speed and lane width.

Mapping architectural register names onto physical value storage.

Making completed instruction effects part of architectural state.

An upper bound connecting compute rate, bandwidth, and arithmetic intensity.

Vector operations and a thread abstraction using grouped lane issue, respectively.

Vendor-specific structures combining scheduling, lanes, and local resources.

Multiple hardware contexts share resources in one physical core.

Integration of processors, controllers, and other system blocks.

Feedback-based state storage that retains data while powered without DRAM-style refresh.

Cached address translations and associated permissions.

An operation rate requiring stated precision, counting, and sparsity conditions.

A group of GPU threads participating in grouped instruction issue.

Physical flash writes exceed host writes because of internal management.