NAND flash & SSD controllers
Retain charge without power, then manage pages, blocks, and wear.
An SSD does not simply overwrite the same physical bytes each time you save a file.
Stores threshold levels.
Make a cache miss
A cache fetches a whole line. Locality reuses it; conflicting mappings can evict useful data even before total capacity is exhausted.
What this model includes
One read-only cache, 64-byte lines, LRU replacement, eight total lines, eight-byte elements, 32 accesses. No prefetching or multilevel effects.
What happens inside
Read pages, erase blocks
NAND stores information through charge-related threshold levels. SLC, MLC, TLC, and QLC encode different bits per cell, trading density against sensing margins, endurance, and performance. Programming works at a page granularity, while erasure affects larger blocks. 3D NAND stacks cells vertically.
Translate and clean up
The flash translation layer maps logical addresses onto physical pages. Wear leveling spreads writes, ECC handles covered errors, and garbage collection reclaims blocks by moving valid pages. TRIM tells the controller which logical ranges no longer need preservation. Internal copying creates write amplification.
What this means for your code
Low-level engineer
Study durability, flush semantics, endurance, and power-loss behavior. Host completion and persistence have specific contracts.
Software developer
Large sequential writes and random small writes exercise different behavior. Maintain spare capacity and measure sustained performance beyond any burst cache.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.