Pipelines & instruction hazards
Overlap stages of different instructions instead of finishing one at a time.
A pipeline improves throughput without making every instruction finish sooner.
Read instruction bytes.
Follow an instruction
Overlap improves throughput. Dependencies introduce bubbles unless the implementation can forward or do independent work.
What this model includes
Five-stage, single-issue teaching model. Dependent mode inserts two idle issue cycles per instruction; real forwarding and hazards vary.
What happens inside
Divide the journey
A teaching pipeline has fetch, decode, execute, memory, and writeback stages. Pipeline registers preserve intermediate state between cycles. Once filled, an ideal single-issue pipeline can finish one instruction per cycle, even if each instruction occupies five cycles. Real pipelines have different depths and issue widths.
Handle hazards
A data hazard occurs when an instruction needs an unfinished result. Forwarding bypasses a later register write when the result is already available. A structural hazard is resource contention; a control hazard comes from a branch. Stalls insert bubbles, while a flush discards wrong-path work.
ideal cycles = stages + instructions − 1What this means for your code
Low-level engineer
Distinguish latency from reciprocal throughput. Load-use delays, forwarding paths, and resource contention depend on the target core.
Software developer
Independent work can overlap; a dependent chain cannot. This is why two loops with the same operation count can run at different speeds.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.