Out-of-order execution & renaming
Run ready work early, then commit the results in program order.
The order you write is the contract for results, not always the order of execution.
Maps names to physical registers.
Follow an instruction
Overlap improves throughput. Dependencies introduce bubbles unless the implementation can forward or do independent work.
What this model includes
Five-stage, single-issue teaching model. Dependent mode inserts two idle issue cycles per instruction; real forwarding and hazards vary.
What happens inside
Remove false dependencies
Writing the same architectural register twice can create name dependencies unrelated to data flow. Renaming maps architectural names onto physical registers, removing write-after-read and write-after-write constraints. A true read-after-write dependency remains: the consumer still needs the producer’s value.
Schedule and retire
Ready operations issue when operands and resources are available. A reorder buffer tracks in-flight operations; retirement commits architectural effects in order. Load/store queues track memory dependencies and may speculate on addresses. A full queue, a long miss, or an unresolved branch bounds the look-ahead window.
What this means for your code
Low-level engineer
Watch instruction-window limits, register pressure, and dependency chains. More unrolling can expose parallelism but also cause spills or instruction-cache pressure.
Software developer
Expose independent computations and use compact data. The core cannot discover unlimited parallelism beyond a blocking dependency or its finite queues.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.