silicon atlasTHE HARDWARE REFERENCE
العربية
Reference/Inside the CPU
CPU & cores

Registers, flags & the stack

Keep live values close, and spill them when physical space runs out.

A variable in your source does not own a permanent hardware register.
Architectural register

A software-visible name.

LIVE EXPERIMENT

Follow an instruction

Runs on your device
12345678910
I1
F
D
E
M
W
I2
F
D
E
M
W
I3
F
D
E
M
W
I4
F
D
E
M
W
I5
F
D
E
M
W
I6
F
D
E
M
W
F · FetchD · DecodeE · ExecuteM · MemoryW · Writeback
Instructions6
Total cycles10
Visible cycle1

Overlap improves throughput. Dependencies introduce bubbles unless the implementation can forward or do independent work.

What this model includes

Five-stage, single-issue teaching model. Dependent mode inserts two idle issue cycles per instruction; real forwarding and hazards vary.

FOLLOW THE MECHANISM

What happens inside

1

Track live values

Architectural registers are named by the ISA. Physical registers are implementation storage used by renaming. The compiler allocates architectural registers to live values and may reuse one when a value dies. Too many simultaneously live values create spills: loads and stores to a stack slot.

2

Respect the call boundary

An ABI divides registers into caller-saved and callee-saved classes and defines argument passing and stack alignment. A call frame may store return state, saved registers, and locals, but optimized code may omit a frame pointer. Status flags hold arithmetic conditions on ISAs that define them.

PUT IT TO WORK

What this means for your code

Low-level engineer

Check calling conventions before mixing languages or assembly. Preserve required registers and stack alignment; an ABI violation can appear far from its cause.

Software developer

Inlining and loop unrolling can increase register pressure. Avoid assuming every local variable creates a memory allocation.

GO TO THE SOURCE

Read the actual specifications

These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.

RISC-V · ISA specificationsRISC-V International
Intel · Optimization reference manualsIntel

Keep following the connection

Understood the idea? Keep a note of your progress.