FPGAs, ASICs & programmable logic
Change the circuit, specialize it permanently, or execute instructions on an existing circuit.
Programming an FPGA describes a circuit, not merely a sequence for a CPU to run.
Configurable logic function.
Build a decision
| A | B | XOR |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
NAND can build any Boolean function. Combining small gates creates selectors, adders, and control.
What this model includes
Ideal Boolean logic. Electrical timing and noise are omitted.
What happens inside
Configure the fabric
An FPGA combines configurable lookup tables, flip-flops, routing, block RAM, and often DSP and high-speed I/O blocks. Configuration bits select functions and connections. HDL describes concurrent hardware behavior; synthesis and place-and-route transform it into a mapped design. Timing closure is part of making it work.
Trade flexibility for efficiency
An ASIC implements a chosen circuit in manufactured silicon, avoiding much of the programmable routing overhead but requiring substantial design and fabrication effort. FPGA logic can build custom pipelines and protocols, but resource, frequency, and power constraints remain. A CPU or GPU instead executes programs within a largely fixed architecture.
What this means for your code
Low-level engineer
Learn HDL semantics, clock-domain crossings, timing constraints, and verification. A simulation passing does not prove timing closure on hardware.
Software developer
FPGAs fit custom streaming and low-latency protocols when development cost is justified. They are not a drop-in faster CPU for arbitrary software.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.