Virtual memory, page tables & TLBs
Translate program addresses into physical pages and enforce permissions.
An address in your process is not simply a location on a RAM chip.
A process-visible location.
Make a cache miss
A cache fetches a whole line. Locality reuses it; conflicting mappings can evict useful data even before total capacity is exhausted.
What this model includes
One read-only cache, 64-byte lines, LRU replacement, eight total lines, eight-byte elements, 32 accesses. No prefetching or multilevel effects.
What happens inside
Translate and protect
A process uses virtual addresses. Page tables map virtual pages onto physical frames and encode permissions. The MMU performs translation, commonly caching recent mappings in a TLB. A TLB miss may cause a hardware page walk; it is not automatically a page fault. Page sizes and table formats depend on the architecture.
Resolve a fault
An absent or disallowed mapping traps to the OS. A minor fault may establish a resident mapping or copy-on-write page without storage I/O. A major fault can require fetching data from storage. Huge pages increase translation reach but have allocation and fragmentation tradeoffs. Virtual address space is not equal to committed physical RAM.
What this means for your code
Low-level engineer
Manage invalidation, permissions, and address-space identifiers correctly. Device DMA may use a separate IOMMU translation path.
Software developer
Working-set size matters more than reserved address space. Touching newly allocated pages can expose costs hidden by allocation timing alone.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.