Performance, efficiency & “super” cores
Different microarchitectures target different performance and power tradeoffs.
“Big”, “prime”, and “super” describe a product strategy, not a new universal type of computation.
Targets responsive heavy work.
Turn up the clock
Dynamic switching power scales roughly with voltage squared and frequency. Leakage, temperature, and idle behavior also matter in real chips.
What this model includes
Normalized dynamic switching power with constant activity and capacitance. Voltage and frequency are independent controls here, unlike a real DVFS operating table.
What happens inside
Understand the design tradeoff
A performance core may spend more area on decode width, speculative execution, caches, and high-frequency paths. An efficiency core targets useful work with a different area/power budget. Either can support the same architectural instructions when the platform defines that compatibility. Efficient does not mean obsolete or unable to multitask.
Match work to a core
Schedulers consider load, responsiveness, affinity, and energy. Migration changes local cache state. A vendor’s “prime” core may use a distinct microarchitecture or a higher-frequency bin of an existing one. You need the exact chip generation, cache sizes, sustained clocks, and power limits to tell which.
What this means for your code
Low-level engineer
Check ISA exposure, affinity APIs, scheduler hints, and per-core counters. Do not assume a permanently fixed core type for every thread.
Software developer
Keep latency-sensitive work short and isolate background work. Validate both plugged-in and battery behavior for the actual device.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.