NICs, packet queues & network I/O
Packets pass through device queues, memory, and CPU scheduling before your code sees them.
A network rate in Gb/s does not tell you how many small packets a core can process.
Sends and receives frames.
Find the bottleneck
Low arithmetic intensity hits the memory ceiling. More data reuse can move the workload toward the compute ceiling.
What this model includes
An ideal upper bound with fixed peak compute and bandwidth. Ignores latency, overhead, cache-level traffic, and instruction mix.
What happens inside
Receive into managed buffers
A NIC receives frames, places data into buffers via DMA, and reports completions. Receive queues can distribute flows across CPUs using hashing and steering. The driver and network stack process descriptors, checksums, and protocol state. Offloads handle selected work, but support and semantics vary.
Balance packets and bytes
Small packets can saturate CPU or queue handling before link bandwidth fills. Interrupt moderation and polling balance throughput and latency. CPU affinity, buffer locality, and RSS placement interact with NUMA. Application copies, serialization, and TLS may dominate once packets reach the process.
What this means for your code
Low-level engineer
Measure drops, queue distribution, IRQ affinity, and per-packet cost. Zero-copy paths still need ownership and lifetime management.
Software developer
Distinguish serialization time, network wait, and CPU processing. Optimize packet batching only within your latency budget.
Read the actual specifications
These references supply the underlying contracts and implementation details. The diagrams here are simplified teaching models.